Marc Snir, Co-Director

Area(s) of Expertise: Parallel Computing Systems, High Performance Computing

One of the primary architects of the NYU Ultracomputer; led the IBM Scalable POWERParallel system development; developer of MPI, the leading API paradigm for distributed memory computing MPI.

Department: Computer Science

Wen-mei Hwu, Co-Director

Area(s) of Expertise: Compiler Design, Computer Architecture, Computer Microarchitecture, Parallel Processing

Leads the design of the IMPACT compiler infrastructure. His team created the first HP-PD compiler, which was used by Intel in the early Itanium design process. Received the Grace Murray Hopper Award and the ACM Maurice Wilkes Award for his contributions to instruction-level parallel processing in compilers, computer architecture, and computer microarchitecture. Leads the MARCO/SRC GSRC Concurrent Theme. One of the original founders and serves on the steering committee of Gelato, a consortium for improving compiler and OS software for Itanium.

Department: Electrical & Computer Engineering

Sarita Adve, Director of Research

Area(s) of Expertise: Computer Architecture and Systems, Parallel Computing, Power Management, Reliability

Co-developer of the memory consistency models for the Java and C++ programming languages, which are based on her PhD thesis work on data-race-free memory models. Other significant contributions include the concepts of lifetime reliability aware architecture and dynamic reliability management, work on cross-layer energy management, exploiting instruction-level parallelism for memory system performance, and multiprocessor simulation methods.

Department: Computer Science

Vikram Adve

Area(s) of Expertise: Compilers, Programming Languages, Computer Architecture, Performance Modeling

Adve's group created the LLVM Compiler Infrastructure, a novel framework for "lifelong" compilation of programs. Developed an elegant "Integer Set Framework" for compiling data- parallel programs, powerful compiler-based techniques for speeding up simulations of large-scale parallel applications, techniques for mapping low-level performance information to high-level parallel language programs, and analytical techniques for predicting performance of parallel programs and systems.

Department: Computer Science

Gul Agha

Area(s) of Expertise: Concurrent Programming Models and Languages, Coordination Languages, Multi-Agent Systems, Methods for Reasoning about Concurrent Programs

Defined the Actor Model, now widely used and a basis for parallel program­ming languages including current languages such as E, Erlang, Ptolemy, and SALSA. Developed compiler and run-time system for efficient parallel actor languages on clusters. Developed high-level coordination and meta-programming languages to support separation of design concerns such as quality of service, dependability and real-time properties. Developed new dynamic techniques for automatic detection of concurrency bugs, and statistical methods for reasoning about quality of service and other probabilistic properties of large-scale concurrent systems.

Department: Computer Science

Eyal Amir

Area(s) of Expertise: Artificial Intelligence, Knowledge Representation & Reasoning, Machine Learning

Co-creator of automatic procedures for distribution and factoring of algorithms, especially those regarding automated reasoning with logic and probabilities, robot control, and decision making. Amir's tracking and state estimation of dynamic systems has led to new directions and approaches in decision making and reinforcement learning in partially observable domains.

Department: Computer Science

David Forsyth

Area(s) of Expertise: Computer Vision, Machine Learning, Computer Graphics

Lead author of “Computer Vision: A Modern Approach,” comprehensive textbook of computer vision that attempts to provide a unified view of the topic, using probabilistic method­ology as the core. The text is used in courses at the University of Wisconsin, USC, Berkeley, Carnegie Mellon, and other top institutions. Received an IEEE Computer Technical Achievement Award in 2005.

Department: Computer Science

Matthew Frank

Area(s) of Expertise: Parallel Computer Architecture and Automatic Parallelizing Compilers

One of the architects of the Raw microprocessor a 16-core processor that taped out in 2002. Recently designed PolyFlow, a reactive, online, automatic parallelization system.

Department: Electrical & Computer Engineering

Maria Garzaran

Area(s) of Expertise: Compilation and Continuous Program Optimization

Generation of library routines for sorting and data mining that adapt to the input, development of analytical models.

Department: Computer Science

John Hart

Area(s) of Expertise: Parallel GPU Algorithms and Computer Graphics

Awarded the first NSF Grant (Revolutionary Computing ITR) for GPGPU, in 2001. Developed Ray Engine, the first GPU implementation of a ray tracer. GPU algorithm work utilized in Microsoft and NVidia products.

Department: Computer Science

Ralph Johnson

Area(s) of Expertise: Software Design, Software Reuse, and Programming Environments.

One of four co-authors of "Design Patterns", a seminal book on software design. Leader of the group that developed the first refactoring tool, the Smalltalk Refactoring Browser. Leader of the group that developed Photran, a widely used open-source Fortran-77 and Fortran-90 IDE.

Worked on frameworks for compilers, operating systems, graphics editors, music generation, network protocol stacks, telephone billing, insurance, and stellar simulation.

Department: Computer Science

Laxmikant Kale

Area(s) of Expertise: Parallel Programming, Dynamic Adaptation, Science and Engineering Applications

Developed Charm++ Parallel Programming System and its ideas of automatic adaptive runtime systems. Co-developed some of the most scalable science and engineering applications, including NAMD for biomolecular simulations, and ChaNGa for gravity simulations in cosmology. Earlier work resulted in some of the most effective strategies for parallel state-space search.

Department: Computer Science

Rakesh Kumar

Area(s) of Expertise: Computer Architecture, Programming/Computing Models

Proposed and studied single-ISA heterogeneous multi-core architectures (or asymmetric multi-core architectures), an architectural solution to adapting to workload diversity. Also, demonstrated that these multi-core architectures can have significantly higher efficiency than conventional processor architectures.

It was the first work in the area of asymmetric multi-core computing that is being widely considered by industry and academia today.

Department: Electrical & Computer Engineering

Darko Marinov

Area(s) of Expertise: Software Testing, Program Analysis and Transformation

Released two open-source tools for testing programs with structurally complex inputs, which found dozens of bugs in Eclipse, NetBeans, and several academic projects. Recent work on parallel test generation and execution done in collaboration with Google.

Department: Computer Science

Klara Nahrstedt

Area(s) of Expertise: Quality of Service Management, Multimedia Systems, QoS-aware Resource Management

Research interests in services and protocols for provision of end-to-end quality of services within distributed multimedia systems. Her research group works on time-variant QoS management, QoS routing, multimedia middleware, peer-to-peer networks, multimedia services for smart rooms, pervasive computing, multimedia operating systems, adaptive cross-layer design of resource management for multimedia mobile systems, and HDTV distribution protocols.

Department: Computer Science

David Padua

Area(s) of Expertise:

Compilers/Library Generators

Contributed to several areas related to parallel computing including auto parallelization, debugging, parallel machine organization, parallel programming languages, parallel algorithms and automatic library generation. His work on coarse-grain parallelization of do loops, race detection using trace analysis and signal processing library generation has been particularly influential. He has long standing collaborations with several faculty members at Illinois as well as members of other institutions including Carnegie-Mellon University, IBM Research, Intel and Purdue University.

Department: Computer Science

Sanjay Patel

Area(s) of Expertise: High-performance processor microarchitecture, Processor reliability

Having recently designed chips for gaming, physical simulation and visualization, Patel is interested in examining many-core processing and accelerator systems for the emerging revolution in visually-oriented, interactive applications.   Patel has extensive industry experience having done architecture, hardware verification, logic design, and performance modeling at Digital Equipment Corporation, Intel Corporation, HAL Computer Systems, Transmeta, and Ageia Technologies. He is currently the Chief Architect and Technologist at Ageia Technologies.

Department: Electrical & Computer Engineering

Grigore Rosu

Area(s) of Expertise: Formal Methods, Language Semantics, Program Analysis

Introduced software runtime verification and monitoring techniques for detecting errors before deployment as well as for avoiding failures after deployment. His Sliced Causality technique, used to filter out irrelevant events from executions of concurrent programs, was shown to detect without any false positives all the concurrency errors found by expensive static analysis techniques. His Monitoring-oriented Programming has been shown to yield systems aware and in control of their own execution with runtime overhead below 10%.

Department: Computer Science

Dan Roth

Area(s) of Expertise: Machine Learning, Natural Language Processing, Inference and Optimization, Information Access Technologies

Roth has made significant contributions to the foundations of machine learning and inference and to the theory and practice of developing learning-centered solutions to natural language problems.

Department: Computer Science

Josep Torrellas

Area(s) of Expertise: Computer Architecture and Systems, Hardware Design, Speculative Multithreading, Hardware and Software Reliability, Low-Power Design

Contributed to the DASH and Cedar experimental parallel computer prototypes. Leader of the I-acoma project, which has made seminal contributions on shared-memory multiprocessor organization, memory hierarchies, and thread-level speculation. The I-acoma project was selected as a Point-Design Study by the government to advance the arrival of petaflop architectures. Co-leader of the FlexRAM Intelligent Memory Architecture and the DARPA-IBM PERCS High-Productivity Multiprocessor projects. Other contributions include architectures to tolerate process variation and novel tools to debug parallel programs. Many of his former PhD students are now leaders in academia and industry.

Department: Computer Science

YuanYuan Zhou

Area(s) of Expertise: Software Dependability, OS and Architecture Support for Dependability

Released several software defect detection tools that have identified hundreds of new bugs in the latest versions of large open source software including Linux, FreeBSD, Apache, etc as well as tens of commercial software. Recent research work focuses on understanding, automatic defect detection, and testing support for parallel programs. A recent innovation from this project, AVIO, is currently under license negotiation with Intel for possible technology transfer to Intel’s Thread Checker.

Department: Computer Science

Craig Zilles

Area(s) of Expertise: microarchitecture, managed languages, profiling, hardware/software co-design, transactional memory

Zilles’ work has demonstrated many techniques for using hardware-software co-design and feedback-directed optimization to optimize performance. Applications range from demonstrating how a multithreaded machine could accelerate a single thread using "helper threads" to prefetch memory and "pre-execute" hard-to-predict branches (ISCA 2001), how a simple transactional memory can be used by a Java virtual machine to perform speculative optimization (ISCA 2007), and to how critical path analysis can be used to mitigate much of the penalty of distributing a sequential execution over a distributed microarchitecture (Micro 2005).

Department: Computer Science