Hardware Architecture
Principal Investigators: Sarita Adve, Vikram Adve, Samuel King, Darko Marinov, Josep Torrellas, Craig Zilles
The arrival of multiprocessors on a chip fundamentally changes many of the parameters for hardware architecture research. We make the following key observations that impact our work:
Hardware must be used for programmability: The goal of much research in hardware architecture has been to provide the best possible cost/performance ratio. Since performance is now achieved by parallel software, it becomes important for the hardware to facilitate the development of such software. Silicon should be increasingly leveraged to support ease of programming.
Hardware must scale in performance, not complexity: As the primary means for performance will be from an increasing number of cores, hardware must be designed to scale in performance but not in complexity. The memory wall will be a major impediment to performance scalability and we must focus attention to memory hierarchy design, communication protocols, and synchronization protocols.Multicore requires new cache protocols: Coherent shared-memory systems either use snooping protocols that scale to a few tens of cores, or use directory protocols that significantly increase memory latency and were originally designed for multi-chip systems with non-uniform memory access. Multicore chips will have hundreds of cores, all accessible with no chip crossings, and all nearly equally afar from the memory DIMMs. This requires new designs.
An opportunity for hardware-software co-design: Complexity in current hardware concurrency mechanisms often arises from a software-oblivious approach. We now have a unique opportunity to rethink the entire system stack and develop hardware that is better aligned with the needs of modern software, including expressing and managing concurrent work units, communication, synchronization, and the memory consistency model.
We are currently pursuing two architecture projects in UPCRC:
The Bulk Multicore project focuses on supporting a flexible substrate with scalable cache coherence, high-performance sequential memory consistency, and an easy-to-use development and debugging environment.
The DeNovo project rethinks concurrent hardware as a co-designed component of our disciplined programming strategy, both for enforcing the discipline and for exploiting it for simpler and more efficient hardware.
- Go to the Hardware Architecture section in the UPCRC whitepaper
- Learn more about The Bulk Multicore.
- Learn more about DeNovo.